DSPIC30F3013-20I/ML【PDF 143/161 页】IC DSPIC MCU/DSP 24K 44QFN

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dsPIC30F2011/2012/3012/3013

DS70139G-page 68

2010 Microchip Technology Inc.

Address Error Trap:

This trap is initiated when any of the following

circumstances occurs:

A misaligned data word access is attempted.

A data fetch from our unimplemented data

memory location is attempted.

A data access of an unimplemented program

memory location is attempted.

An instruction fetch from vector space is

attempted.

Execution of a “BRA #literal” instruction or a

“GOTO #literal” instruction, where literal

is an unimplemented program memory address.

Executing instructions after modifying the PC to

point the unimplemented program memory

addresses. The PC may be modified by loading

a value into the stack and executing a RETURN

instruction.

Stack Error Trap:

This trap is initiated under the following conditions:

The Stack Pointer is loaded with a value which is

greater than the (user programmable) limit value

written into the SPLIM register (stack overflow).

The Stack Pointer is loaded with a value which is

less than 0x0800 (simple stack underflow).

Oscillator Fail Trap:

This trap is initiated if the external oscillator fails and

operation becomes reliant on an internal RC backup.

8.3.2

HARD AND SOFT TRAPS

It is possible that multiple traps can become active

within the same cycle (e.g., a misaligned word stack

write to an overflowed address). In such a case, the

fixed priority shown in Figure 8-2 is implemented,

which may require the user to check if other traps are

pending, in order to completely correct the Fault.

Soft traps include exceptions of priority level 8 through

level 11, inclusive. The arithmetic error trap (level 11)

falls into this category of traps.

Hard traps include exceptions of priority level 12

through level 15, inclusive. The address error (level

12), stack error (level 13) and oscillator error (level 14)

traps fall into this category.

Each hard trap that occurs must be acknowledged

before code execution of any type can continue. If a

lower priority hard trap occurs while a higher priority

trap is pending, acknowledged, or is being processed,

a hard trap conflict occurs.

The device is automatically Reset in a hard trap conflict

condition. The TRAPR Status bit (RCON<15>) is set

when the Reset occurs, so that the condition may be

detected in software.

Note:

In the MAC class of instructions, wherein

the data space is split into X and Y data

space, unimplemented X space includes

all of Y space, and unimplemented Y

space includes all of X space.

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